Backside contacts for integrated circuit devices

ABSTRACT

A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 14/968,124, entitled “Backside Contacts for Integrated Circuit Devices,” filed on Dec. 14, 2015, which application is a divisional of U.S. patent application Ser. No. 14/021,881, entitled “Backside Contacts for Integrated Circuit Devices,” filed on Sep. 9, 2013, now U.S. Pat. No. 9,214,398 issued Dec. 15, 2015, which application is incorporated herein by reference.

BACKGROUND

In the formation of integrated circuits, transistors are often formed in well regions, which include p-well regions and n-well regions. The well regions are typically applied with bias voltages, or electrically grounded. In order to apply the bias voltages, pickup regions and the respective contact plugs are formed to connect to the well region. The pickup regions are heavily doped semiconductor regions at the surfaces of the well regions. A p-well region has a heavily doped p-type pickup region, and an n-well region has a heavily doped n-type pickup region.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 6 are cross-sectional views of intermediate stages in the manufacturing of a first chip/wafer in accordance with some exemplary embodiments, wherein the first chip includes backside well pickup regions connected to well regions;

FIGS. 7 through 10 are cross-sectional views of intermediate stages in the bonding of the first chip/wafer to a second chip/wafer and the continued formation of the first chip/wafer in accordance with some exemplary embodiments; and

FIG. 11 illustrates a flow chart for forming a package in accordance with some embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.

A package with a chip that has backside body contacts and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the package are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 11 illustrates flow chart 300 for forming a package in accordance with some embodiments, wherein the process steps illustrated in FIGS. 1 through 10 are discussed referring to the steps shown in FIG. 11. FIGS. 1 through 6 are cross-sectional views of intermediate stages in the manufacturing of parts of a first chip in accordance with some exemplary embodiments. Referring to FIG. 1, wafer 100 is provided. Wafer 100 includes semiconductor substrate 102, which may be a silicon substrate in some embodiments. In alternative embodiments, semiconductor substrate 102 is formed of other semiconductor materials such as silicon germanium, silicon carbon, III-V compound semiconductors, or the like. Semiconductor substrate 102 is a bulk substrate that is formed of a homogeneous material, which means that the entire semiconductor substrate 102 is formed of a same semiconductor material such as silicon, silicon germanium, silicon carbon, III-V compound semiconductors, and the like.

P-well region 104 and N-well region 108 are formed in semiconductor substrate 102 (step 302 in FIG. 11). In some embodiments, P-well region 104 and N-well region 108 extend from back surface 102B to an intermediate level of semiconductor substrate 102. In some embodiments, P-well region 104 and N-well region 108 have the respective p-type and n-type impurity concentrations in the range between about 1E14/cm³ and 1E17/cm³, although higher or lower impurity concentrations may also be used. It is appreciated, however, that the values recited throughout the description are merely examples, and may be changed to different values.

P-well pickup region 106 and N-well pickup region 110 are formed over P-well region 104 and N-well region 108, respectively (step 302 in FIG. 11), for example, through implanting the surface portions of P-well region 104 and N-well region 108, respectively. P-well pickup region 106 and N-well pickup region 110 are heavily doped regions with the respective p-type and n-type impurity concentrations higher than about 1E19/cm³. The impurity concentrations in the heavily doped regions 106 and 110 may also be in the range between about 1E19/cm³ and 1E21/cm³. In accordance with some embodiments, P-well pickup region 106 and N-well pickup region 110 cover parts, but not all, of the respective P-well region 104 and N-well region 108. In alternative embodiments, an entirety of one of P-well region 104 and N-well region 108 is covered by the respective P-well pickup region 106 and N-well pickup region 110, which means that the edges of P-well pickup region 106 and N-well pickup region 110 extend to the edges of the respective P-well region 104 and N-well region 108. The P-well pickup region 106 and N-well pickup region 110 in these embodiments are marked as 106′ and 110′, respectively.

In some embodiments, sacrificial layer 112 is formed. Sacrificial layer 112 may be formed before or after the formation of regions 104, 106, 108, and 110, and is formed to reduce the damage caused by the implantations for forming regions 104, 106, 108, and 110. Sacrificial layer 112 may be a silicon oxide layer in some embodiments. The formation of sacrificial layer 112 includes, for example, thermal oxidation or a deposition using Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), or the like.

Referring to FIG. 2, hydrogen implantation 114 is performed to implant hydrogen ions into substrate 102 (step 304 in FIG. 11), so that hydrogen-concentrated layer 116 is formed in substrate 102. The implantation is performed from the backside (the side facing up in FIG. 2) of wafer 100 in some embodiments. Hydrogen-concentrated layer 116 may extend into the bottom portions of P-well region 104 and N-well region 108 in some embodiments. In alternative embodiments, the top surface of hydrogen-concentrated layer 116 is either coplanar with or lower than the bottom surfaces of P-well region 104 and N-well region 108. The top surface of hydrogen-concentrated layer 116 may also be lower than the bottom surfaces of P-well pickup region 106 and N-well pickup region 110 in yet alternative embodiments.

After the hydrogen implantation, sacrificial layer 112 is removed, and wafer 100 is mounted on carrier 118 (step 306 in FIG. 11), as shown in FIG. 3. The back surface 102B of substrate 102 faces toward carrier 118. Carrier 118 may be a glass carrier, a ceramic carrier, or the like. In some embodiments, wafer 100 is mounted on carrier 118 through adhesive 120, which may be an Ultra Violet (UV) glue. Next, as shown in FIG. 4, wafer 100 is cleaved to separate the portion overlying hydrogen-concentrated layer 116 and the portion underlying hydrogen-concentrated layer 116 (step 308 in FIG. 11). The respective method is sometimes referred to as a smart cut, which may include annealing wafer 100 at an elevated temperature such as about 350° C. to about 450° C., and/or applying sideway mechanical forces in the directions parallel to the top surface of wafer 100. After the smart cut, a planarization such as a Chemical Mechanical Polish (CMP) is performed to remove remaining hydrogen-concentrated layer 116, and to level front surface 102A of substrate 102. After the planarization, P-well region 104 and N-well region 108 are exposed. As a result, P-well region 104 and N-well region 108 penetrate through the remaining substrate 102.

Next, referring to FIG. 5, integrated circuit devices, which may include transistors, diodes (not shown), resistors (not shown), or the like, are formed. FIG. 5 schematically illustrates the formation of n-type Metal Oxide Semiconductor (nMOS) transistor 122 and p-type MOS (pMOS) transistor 132 (step 312 in FIG. 11) in P-well region 104 and N-well region 108, respectively. In some embodiments, nMOS transistor 122 includes gate electrode 124, gate dielectric 126, and source and drain regions 128, which are heavily doped n-type regions. PMOS transistor 132 includes gate electrode 134, gate dielectric 136, and source and drain regions 138, which are heavily doped p-type regions. Source/drain regions 128 and 138 may have n-type and p-type impurity concentrations in the range between about 1E19/cm³ and 1E21/cm³. Throughout the description, the side 102A of substrate 102, at which side the integrated circuit devices 122/132 are formed, is referred to as the front surface of substrate 102 and the front surface of wafer 100, and the opposite surface 102B is referred to as a back surface of substrate 102 and the back surface of wafer 100.

Referring to FIG. 6, source/drain silicide regions 140 are formed at the top surfaces of source/drain regions 128 and 138, and source/drain contact plugs 142 are formed over and in contact with source/drain silicide regions 140. Furthermore, interconnect structure 144 is formed (step 312 in FIG. 11). Interconnect structure 144 includes dielectric layers 145, and metal lines 146 and vias 148 formed in dielectric layers 145. Dielectric layers 145 may include an Inter-Layer Dielectric (ILD), Inter-Metal Dielectric (IMD) layers, passivation layers, and the like. Front surface 102A of substrate 102 is thus in contact with the overlying dielectric layer 145, which may be a contact etch stop layer or the ILD, for example. The ILD layer and the IMD layers may be low-k dielectric layers in some embodiments, which have dielectric constants (k values) lower than about 3.5, lower than about 3.0, or lower than about 2.5. Dielectric layers 145 may also include non-low-k dielectric materials having dielectric constants (k values) equal to or greater than 3.8. Metal lines 146 and vias 148 may include copper, aluminum, nickel, tungsten, or alloys thereof. Metal lines 146 and vias 148 interconnect the integrated circuit devices such as transistors 122 and 132, and may electrically couple the integrated circuit devices to the overlying metal features 152.

In some embodiments, interconnect structure 144 includes surface dielectric layer 150, which is formed at the surface of wafer 100. Surface dielectric layer 150 may be a silicon-containing dielectric layer, which may comprise silicon oxide (SiO₂), silicon oxynitride (SiON), silicon nitride (SiN), or the like. Metal pads 152 are formed in surface dielectric layer 150, and may be electrically coupled to devices 122/132 through metal lines 146 and vias 148. Metal pads 152 may also be formed of copper, aluminum, or alloys thereof. The top surface of surface dielectric layer 150 and the top surfaces of metal pads 152 may be substantially coplanar with each other.

FIG. 7 illustrates the bonding of wafer 100 to wafer 200 (step 314 in FIG. 11). Wafer 200 may be selected from a device wafer, an interposer wafer, and the like. In the illustrated FIG. 7, wafer 200 includes substrate 202, P-well region 204, N-well region 208, P-well pickup region 206, N-well pickup region 210, active devices 222/232, dielectric layers 245, metal lines 246 and vias 248 in dielectric layers 245, surface dielectric layer 250, and metal pads 252. Wafer 200 may have a structure similar to what is described for wafer 100, and the details are not repeated herein. The materials of the features in wafer 200 may be found referring to the like features in wafer 100. The features in wafer 200 are marked with reference numerals starting with number “2,” which features correspond to the like features in wafer 100 and having similar reference numerals starting with number “1.”

In some embodiments, P-well pickup region 206 and N-well pickup region 210 are formed at the front surface 202A of substrate 202. In alternative embodiments, P-well pickup region 206 and N-well pickup region 210 are formed at the bottom surfaces of well pickup region 206 and N-well pickup region 210, respectively. In which embodiments, further process steps may be performed to electrically couple to P-well pickup region 206 and N-well pickup region 210 from the backside (the bottom side in FIG. 7) of wafer 200.

Carrier 118 and glue 120 are removed, and the respective structure is shown in FIG. 8. Back surface 102B of substrate 102 is exposed. P-well region 104, N-well region 108, P-well pickup region 106, and N-well pickup region 110 are also exposed. Next, as shown in FIG. 9, dielectric layer 154 is formed over and contacting the back surface 102B of substrate 102. Body silicide regions 156 may be formed at the top surfaces of P-well pickup region 106 and N-well pickup region 110. Body contact plugs 158 are formed in dielectric layer 154 to connect to body silicide regions 156. Throughout the description, each of well pickup region 106 and N-well pickup region 110 is referred to as a backside contact structure. The backside contact structure may also include the respective overlying silicide regions 156 and contact plugs 158.

In addition, Inter-Layer Vias (ILV) 162 are formed to electrically connect to metal line/pads 146 on the front side of substrate 102 (step 316 in FIG. 11). Throughout the description, ILVs 162 are also referred to as through-vias. Isolation layers 160 are formed to encircle ILVs 162, so that ILVs 162 are electrically decoupled from substrate 102. The formation process may include etching dielectric layer 154, substrate 102, and dielectric layer 145 to form openings, filling an isolation layer in the openings, and removing the bottom portions of the isolation layer in the openings to expose metal lines/pads 146. A metallic material is then filled into the openings, followed by a CMP. The remaining portions of the isolation layer and the metallic material in the openings form isolation layers 160 and ILVs 162, respectively.

FIG. 10 illustrates the formation of interconnect structure 164 on the backside of substrate 102 (step 318 in FIG. 11). Interconnect structure 164 may include dielectric layers 166, and metal lines 168 and vias 170 in dielectric layers 166. Dielectric layers 166 may include low-k dielectric layers, passivation layers, and the like. The low-k dielectric layers may have dielectric constants (k values) lower than about 3.5, lower than about 3.0, or lower than about 2.5. Dielectric layers 166 may also include non-low-k dielectric materials having dielectric constants (k values) equal to or greater than 3.8. Metal lines 168 and vias 170 may include copper, aluminum, nickel, tungsten, or alloys thereof. Through contact plugs 142, ILVs 162, and metal lines 168, the source/drain silicide regions 140 are electrically connected to the respective backside body contacts 106/110/156/158, so that the backside body contacts may have same voltage levels as the respective source and drain regions that are in the same well regions.

In some embodiments, Under-Bump Metallurgies (UBMs) 174 are formed, and electrical connectors 176 are formed on UBMs 174. Electrical connectors 176 may include solder balls, copper bumps, or the like. Electrical connectors 176 may be electrically connected to the integrated circuit devices (such as 122/132) in wafer 100 and the integrated circuit devices 222/232 in wafer 200, for example, through ILVs 162.

After the formation of the bonded wafers 100 and 200, a die-saw may be performed, and wafer 100 and 200 are sawed into a plurality of packages 400, each including one of chips 100′ in wafer 100, and one of chips 200′ in wafer 200. Packages 400 may then be bonded to other package components such as interposers, package substrates, printed circuit boards, or the like.

The embodiments of the present disclosure have several advantageous features. Since the body contacts of the well regions are formed on the backside of the substrates, they can overlap the respective devices such as transistors. Accordingly, the body contacts do not take extra chip area, and hence the chip area usage is improved. Furthermore, with the backside body contacts, the efficiency in in the body pickup is improved over that of the front-side body contacts, and hence the efficiency in the Electro-Static Discharge (ESD) performance and the resistance to the latch-up of the respective package is improved.

In accordance with some embodiments, a chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.

In accordance with other embodiments, an integrated circuit structure includes a semiconductor substrate, a well region extending from a front surface of the semiconductor substrate to a back surface of the semiconductor substrate, and a well pickup region in the well region and extending from the back surface of the semiconductor substrate into the semiconductor substrate. The well pickup region and the well region are of a first conductivity type. A first silicide region contacts a surface of the well pickup region. A heavily doped semiconductor region is in the well region and extends from the front surface of the semiconductor substrate into the semiconductor substrate. The heavily doped semiconductor region is of a second conductivity type opposite to the first conductivity type. A second silicide region contacts a surface of the heavily doped semiconductor region. Metallic features connect the first silicide region to the second silicide region.

In accordance with yet other embodiments, a method includes forming a well region extending from a back surface of a semiconductor substrate into the semiconductor substrate, forming a well pickup region extending from the back surface of the semiconductor substrate into the well region, and forming a transistor at a front surface of the well region. The front surface of the well region is comprised in a front surface of the semiconductor substrate. The step of forming the transistor includes forming a source/drain region at the front surface of the well region, and forming a source/drain silicide region contacting the source/drain region. Metallic features are formed to electrically inter-couple the well pickup region and the source/drain silicide region.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. 

What is claimed is:
 1. An integrated circuit structure comprising: a first chip comprising: a semiconductor substrate; a well region extending from a top surface to a bottom surface of the semiconductor substrate; a well pickup region in the well region and overlapping a portion of the well region; a transistor comprising: a gate stack underlying the semiconductor substrate; and a source/drain region adjacent to the gate stack; a through-via penetrating through the semiconductor substrate, wherein the through-via electrically connects the source/drain region to the well pickup region; an isolation layer encircling and contacting the through-via, wherein the semiconductor substrate encircles, and is in contact with, the isolation layer; and a dielectric layer, with the gate stack being in the dielectric layer, and the through-via further penetrates through the dielectric layer.
 2. The integrated circuit structure of claim 1, wherein both the well pickup region and the source/drain region are in the well region, and the well pickup region extends to a top surface of the semiconductor substrate.
 3. The integrated circuit structure of claim 1 further comprising a second chip bonded to the first chip, wherein the second chip and the gate stack are on a same side of the semiconductor substrate.
 4. The integrated circuit structure of claim 1 further comprising an additional dielectric layer encircling the through-via, wherein the dielectric layer and the additional dielectric layer are on opposite sides of the semiconductor substrate.
 5. The integrated circuit structure of claim 1 further comprising: a silicide region at a top surface of, and contacting, the well pickup region; and a contact plug over and contacting the silicide region, wherein the contact plug is level with a portion of the through-via.
 6. The integrated circuit structure of claim 1, wherein the through-via is tapered, with upper portions of the through-via being wider than respective lower portions of the through-via.
 7. The integrated circuit structure of claim 1, wherein the well region penetrates through the semiconductor substrate.
 8. The integrated circuit structure of claim 1, wherein the well region comprises a top surface and a bottom surface, both being in contact with dielectric materials.
 9. An integrated circuit structure comprising: a first chip comprising a semiconductor substrate; a well region extending from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate; a first silicide region at a top surface of the semiconductor substrate, wherein the well region has portions on opposite sides of the first silicide region; a transistor comprising: a gate stack overlapped by the well region; and a source/drain region extending from a bottom surface of the semiconductor substrate up into the well region; a second silicide region contacting a bottom surface of a portion of the source/drain region; and a through-via penetrating through the semiconductor substrate, wherein the through-via electrically interconnects the first silicide region and the second silicide region, wherein the through-via is tapered, with a first end of the through-via close to the top surface of the semiconductor substrate being wider than a second end of the through-via close to the bottom surface of the semiconductor substrate.
 10. The integrated circuit structure of claim 9 further comprising a well pickup region in the well region, wherein the first silicide region is at a top surface of the well pickup region.
 11. The integrated circuit structure of claim 9 further comprising a second chip underlying and bonded to the first chip.
 12. The integrated circuit structure of claim 9 further comprising: a first dielectric layer contacting the top surface of the semiconductor substrate; and a second dielectric layer contacting the bottom surface of the semiconductor substrate, wherein the through-via further penetrates through both the first dielectric layer and the second dielectric layer.
 13. The integrated circuit structure of claim 12, wherein the first dielectric layer is in contact with the well region.
 14. The integrated circuit structure of claim 12, wherein the through-via further extends higher than the first dielectric layer and lower than the second dielectric layer.
 15. The integrated circuit structure of claim 9, wherein the through-via is tapered, with upper portions being wider than respective lower portions.
 16. The integrated circuit structure of claim 9 further comprising a dielectric isolation layer encircling the through-via, wherein the dielectric isolation layer has a first end level with the first end of the through-via, and a second end level with the second end of the through-via.
 17. The integrated circuit structure of claim 9, wherein the through-via has a portion at a same level as the gate stack.
 18. An integrated circuit structure comprising: a semiconductor substrate comprising a top surface and a bottom surface; a Metal-Oxide Semiconductor (MOS) device comprising: a gate dielectric underlying the semiconductor substrate, wherein the gate dielectric contacts the bottom surface of the semiconductor substrate; a gate electrode underlying the gate dielectric; and a source/drain region on a side of the gate electrode; a well region extending from the top surface to the bottom surface of the semiconductor substrate, with the source/drain region having a part in the well region; a well pickup region contacting a top surface of the well region, wherein the well pickup region overlaps a part of the MOS device; a through-via penetrating through the semiconductor substrate, wherein the through-via electrically connects the well pickup region to the source/drain region; a dielectric layer over and contacting the top surface of the semiconductor substrate, wherein the through-via further penetrates through the dielectric layer; and a contact plug in the dielectric layer, wherein the contact plug electrically couples the well pickup region to the through-via.
 19. The integrated circuit structure of claim 18 further comprising: an inter-layer dielectric underlying the semiconductor substrate, wherein the gate electrode of the MOS device is in the inter-layer dielectric, and the through-via further penetrates through the inter-layer dielectric.
 20. The integrated circuit structure of claim 18, wherein the through-via has a top width and a bottom width smaller than the top width. 